The present invention relates to a semiconductor device comprising a transistor composing a logic circuit and transistors composing input/output circuits and to a method for fabricating the same.
In a semiconductor device comprising a transistor (hereinafter referred to as a core transistor) composing a logic circuit and transistors (hereinafter referred to as I/O transistors) composing input/output circuits, the individual transistors typically has different power source voltages corresponding thereto, respective gate insulating films with different thicknesses, different impurity profiles, and the like.
Since the core transistor is required to achieve both low power consumption and high-speed operation, the power source voltage thereof is set lower than that of each of the I/O transistors and the gate insulating film thereof is formed to be thinner than that of the I/O transistor. On the other hand, both of the core transistor and the I/O transistors have identically configured source/drain regions. In each of the I/O transistors, lightly doped diffusion layers termed LDD regions are formed in the portions of the source/drain regions which are interposed between the source and the drain. In the core transistor, heavily doped SD extension regions are formed to have shallow junctions. In general, a process which forms gate insulating films with two different thicknesses in a semiconductor device is termed a dual-oxide process.
In recent years, there have been cases where not only one type of I/O transistor but also two types of I/O transistors which achieve higher-speed operation and lower power consumption have been in demand. In such cases, it is necessary to set the power source voltage of a second-type I/O transistor to a value lower than that of a first-type I/O transistor and also form the gate insulating film of the second-type I/O transistor such that it is thinner than that of the first-type I/O transistor. This necessitates the introduction of a triple-oxide process for forming the core transistor and the two types of I/O transistors.
A method for optimizing the power source voltages and the thicknesses of the gate insulating films in such a triple-oxide process depending on the uses and applications of the transistors composing a semiconductor device is disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2001-24168.
FIG. 4 is a cross-sectional view showing the structure of a conventional semiconductor device produced by using a triple-oxide process. As shown in FIG. 4, the conventional semiconductor device is provided with a core transistor Tr1 and two I/O transistors Tr2 and Tr3 which are different in type and power source voltage. The respective thicknesses Tox1, Tox2, and Tox3 of the gate insulating films 106a, 104a, and 103a in the individual transistors Tr1 to Tr3 satisfy Tox1<Tox2<Tox3. The junction depth Xj1 of each of the SD extension regions 111 of the core transistor Tr1 and the respective junction depths Xj2 and Xj3 of the LDD regions 112 and 113 of the I/O transistors Tr2 and Tr3 satisfy Xj1<Xj2<Xj3. The respective peak concentrations N1, N2, and N3 of the SD extension regions 111 and the LDD regions 112 and 113 satisfy N1>N2>N3.
FIGS. 5A to 5E and FIGS. 6A to 6D are cross-sectional views illustrating the steps of the triple-oxide process for forming the gate insulating films in the semiconductor device shown in FIG. 4. In accordance with the method, a silicon oxide film 103 with a thickness required for the gate insulating film of the I/O transistor Tr3 is formed first over the entire surface of a semiconductor substrate 101 in the step shown in FIG. 5A. Then, a resist mask 120 for forming openings corresponding to regions to be formed with the core transistor Tr1 and the I/O transistor Tr2 is formed. Subsequently, in the step shown in FIG. 5B, wet etching is performed to remove the portions of the silicon oxide film 103 which are exposed in the openings, thereby forming the gate insulating film 103a for the I/O transistor Tr3. Thereafter, the resist mask 120 is removed.
Next, in the step shown in FIG. 5C, a silicon oxide film 104 with a thickness required for the gate insulating film of the I/O transistor Tr2 is formed on the semiconductor substrate 101. Subsequently, in the step shown in FIG. 5D, a resist mask 105 for forming an opening corresponding to the region to be formed with the core transistor Tr1 is formed. Then, in the step shown in FIG. 5E, wet etching is performed to remove the portion of the silicon oxide film 104 which is exposed in the opening, thereby forming the gate insulating film 104a for the I/O transistor Tr2.
Next, in the step shown in FIG. 6A, the gate insulating film 106a for the core transistor Tr1 is formed. Then, a polysilicon film 107 is formed over the gate insulating films 103a, 104a, and 106a. 
Next, in the step shown in FIG. 6B, the polysilicon film 107 is patterned to form gate electrodes 108, 109, and 110.
Next, in the step shown in FIG. 6C, the SD extension regions 111 and LDD regions 112 and 113 of the individual transistors Tr1 to Tr3 are formed in the step shown in FIG. 6C. Since doses and implant energies for the SD extension regions 111 and the LDD regions 112 and 113 are different from each other, the three types of regions are formed individually by different ion implantation processes. Specifically, the steps of covering, for the formation of one type of the SD extension regions 111 and the LDD regions 112 and 113, the other two types of the regions with a resist mask (not shown), implanting impurity ions in the state in which the other two types of the regions are covered with the resist mask, and then removing the resist mask are repeated three times.
Then, in the step shown in FIG. 6D, L-shaped first sidewalls 114 are formed on the side surfaces of the gate electrodes 108, 109, and 110 and second sidewalls 115 are formed to be located on the first sidewalls 114. Thereafter, ion implantation is performed by using the gate electrodes 108, 109, and 110 and the first and second sidewalls 114 and 115 as a mask, thereby forming source/drain regions 116.
However, the triple-oxide process described above has encountered the problems of higher cost and the like resulting from complicated process steps.